1. Field of the Invention
The present invention relates generally to a multiple-gate metal oxide semiconductor (MOS) transistor and a method of manufacturing the same, and more particularly to a multiple-gate MOS transistor having a channel in a form of a streamline (∩), and a source and a drain in which a series resistance is reduced, and a method of manufacturing the same.
2. Discussion of Related Art
As technology for manufacturing a semiconductor device is developed, many efforts have been made to improve performance of the semiconductor device through a decrease in size, an increase in operating speed, and so on. Hence, in the case of a metal-oxide-semiconductor field-effect transistor (MOSFET) which has constituted the principal axis of devices used in the electronic field today, the size decrease (scale down) has been continued. However, when a length of a channel decreases to 100 nm or less, the MOSFET is generally lowered in ON/OFF control capability depending on a gate voltage due to a so-called short channel effect.
In order to overcome the problem, there has been a proposal for a dual-gate structure where gate electrodes are formed on both sides of the channel through which an electric current flows. Since the gate electrodes are formed on the both sides of channel in the dual-gate structure, the capability of controlling the electric current in the channel is significantly improved by means of the gate voltage. Thus, the short channel effect is suppressed, so that it is possible to more reduce the size of the device. In addition, there has been a proposal for either a “wrap-around” gate structure or a “surround” gate structure which expands a concept of the dual-gate structure. In these gate structures, the control capability depending on the gate voltage could be improved.
In the FET of the ideal dual-gate structure, the front side and back side gates are self-aligned and source and drain are also self-aligned, and thus a parasitic resistance becomes small. Recently, a FinFET of the dual-gate structure has been developed, which has a self-aligned gate while applying the existing semiconductor process as it is. It has an advantage of the high compatibility with the existing planar structure semiconductor technologies.
FIG. 1 is a perspective view for explaining a conventional dual-gate FinFET.
A silicon on insulator (SOI) substrate on which a silicon layer 10, an oxide layer 11, and a single-crystal silicon layer 12 are laminated is used. Source and drain regions 12a, a channel region 12b, and an expansion region 12c are defined by a single-crystal silicon pattern 12 which is formed by patterning the single-crystal silicon layer 12 and has a fin structure. The channel region 12b and the expansion region 12c between the source and drain regions 12a are formed to be narrower than the source and drain regions 12a. 
A mask pattern 13 for preventing concentration of an electric field and formation of a channel is formed on the single-crystal pattern 12 of the channel region 12b, and a gate oxide layer 14 is formed on the single-crystal silicon pattern 12, and a gate electrode 15 is formed on the gate oxide layer 14 and an oxide layer 11 of the channel region 12b. 
However, the dual-gate FinFET configured as mentioned above has the following disadvantages.
First, in order to manufacture the FinFET in which a gate length is about 60 nm and an operating characteristic is stabilized, the channel region should be formed to a width of about 40 nm or less. But, in order to form the channel with a fine size, nano-patterning technology is required, and thus precise lithography technology is required. When general electronic beam lithography technology is used, the characteristic deviation of the device may be relatively increased because the change of the width of the channel region becomes relatively increased.
Second, when forming the fin having the single crystal silicon pattern as mentioned above, it is difficult to form the pattern to be thin and high and the fin of the channel region is formed in a rectangular shape. For these reasons, there occurs a corner effect in which electrons are accumulated by local concentration of the electric field at an upper end edge, and thus the reliability of the device becomes lowered.
Finally, since the source and drain expansion region is formed to the same thickness as the channel region, a parasitic resistance becomes higher, and thus the electric current driving capability of the device is significantly decreased. In order to solve these problems, an attempt has been made to apply elevated source and drain structures in which single-crystal silicon or silicon germanium (SiGe) is epitaxially grown in source and drain regions. However, this attempt has a problem of making its process complicated.